A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before...

Vulnerability Description

A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability.

References

• https://github.com/chipsalliance/rocket-chip.git
• https://github.com/107040503/RISC-V-Vulnerability-Disclosure_SRET