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Status published
Unknown
CVE-2025-45006
Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit...
Vulnerability Description
Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks.
Impact Analysis
Refer to official advisory for detailed impact metrics.
Remediation
Ensure systems are updated to the latest vendor-supplied patch levels.
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Credits & Attribution
No credits recorded in the NVD database.
References
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Affected Vendor
Affected Software
Unknown
Vulnerable Versions:
Unknown
Timeline
Official Publish:
July 1st, 2025
Last Modified:
July 2nd, 2025
Added to House:
July 22nd, 2026
CVSS Vectors
No vector data available
Weaknesses (CWE)
No CWE data available
MITRE ATT&CK TTPs
No associated TTPs found for this vulnerability.