Back to Database
Status published
Medium
CVE-2020-0574
Improper configuration in block design for Intel(R) MAX(R) 10 FPGA...
Vulnerability Description
Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to potentially enable escalation of privilege and information disclosure via physical access.
Impact Analysis
Refer to official advisory for detailed impact metrics.
Remediation
Ensure systems are updated to the latest vendor-supplied patch levels.
THREAT MONITOR
Am I Vulnerable?
Launch our assessment wizard to check if your infrastructure is exposed to • CVE-2020-0574
Credits & Attribution
No credits recorded in the NVD database.
More from Intel
View All →CVE-2023-50197
Intel Driver & Support Assistant Link Following Local Privilege Escalation Vulnerability
High
7.8
CVE-2023-42099
Intel Driver & Support Assistant Link Following Local Privilege Escalation Vulnerability
High
7.8
CVE-2022-29901
Arbitrary Memory Disclosure through CPU Side-Channel Attacks (Retbleed)
Medium
5.6
CVE-2020-0583
Improper access control in the subsystem for Intel(R) Smart Sound...
High
8.8
CVE-2020-0567
Improper input validation in Intel(R) Graphics Drivers before version 26.20.100.7212...
Medium
5.5
Affected Vendor
Intel
View all reports →Affected Software
Intel(R) MAX(R) 10 FPGA
Vulnerable Versions:
All versions, See advisory https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00349.html
Timeline
Official Publish:
March 12th, 2020
Last Modified:
August 4th, 2024
Added to House:
July 21st, 2026
CVSS Vectors
V3:
CVSS:3.1/AV:P/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:N
Weaknesses (CWE)
No CWE data available
MITRE ATT&CK TTPs
No associated TTPs found for this vulnerability.